1. Field of the Invention
The present invention relates to a semiconductor device including a MOS-type transistor and a manufacturing method thereof. The present invention particularly relates to a semiconductor including a MOS-type transistor in which silicon selective growth layers including impurity diffusion layers are provided in a step-like (elevated) shape on both sides of a gate electrode, and a manufacturing method thereof.
Priority is claimed on Japanese Patent Application No. 2007-182359, filed Jul. 11, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
In MOS-type transistors, the short channel effect must be suppressed to achieve miniaturization, i.e. to shorten the gate length. To reduce the junction depth of the source and drain regions (depth from the substrate surface) and suppress reduction of the on-current, resistance must be suppressed.
To meet such demands, a transistor with an elevated source/drain structure, in which a step-like (elevated) silicon selective growth layer is provided in a source region and a drain region of a silicon substrate, is proposed (e.g. Japanese Unexamined Patent Application, First Publication No. H 10-50989, Japanese Unexamined Patent Application, First Publication No. 2000-49348, Japanese Unexamined Patent Application, First Publication No. 2004-6891). In such transistors, when fabricating the source region and the drain region, ions are implanted from a top face of the silicon selective growth layer. This enables the source and drain regions to be fabricated thinner by the same thickness as the silicon selective growth layer, while utilizing conventional ion-implantation conditions. A transistor in which short channel effect is unlikely to arise can thus be obtained. It also becomes possible to fabricate source and drain regions in a diffusion layer region of higher concentration, thereby reducing the parasite resistance and increasing the on-current.
FIG. 14 is an example of a transistor with an elevated source/drain structure of related art. The transistor in FIG. 14 is an n-channel transistor that uses electrons as carriers. In this transistor, a gate electrode 103 is formed over a p-type silicon substrate 101, with a gate insulation film 102 therebetween. An upper gate insulation film 104 is provided on a top face of the gate electrode 103. Side walls 105 made of insulation film are formed at side faces of the gate electrode 103.
Diffusion layer regions including first diffusion layer regions 106a and 106b to fourth diffusion layer regions 109a and 109b are provided respectively at both side faces of gate electrode formation regions (regions corresponding to gate electrodes) of the silicon substrate 101. The first diffusion layer regions 106a and 106b are n-type impurity diffusion layers, provided in regions that correspond to the side walls 105 of the silicon substrate 101. The first diffusion layer regions 106a and 106b function as extension regions that constitute a lightly doped drain (LDD) structure. In this transistor, a region between these first diffusion layer regions 106a and 106b becomes a channel region 110 which carriers flow through.
The fourth diffusion layer regions 109a and 109b are p-type impurity diffusion layers, provided around the first diffusion layer regions 106a and 106b and third diffusion layer regions 108a and 108b of the silicon substrate 101. The fourth diffusion layer regions 109a and 109b function as halo regions that prevent punch-through and the like. Step-like (elevated) silicon selective growth layers 110a and 110b are fabricated by selective epitaxial (EPI) growth on both sides of the gate electrode 103 (at regions corresponding to the third diffusion layer regions 108a and 108b) on the silicon substrate 101.
Second diffusion layer regions 107a and 107b are provided in approximately the whole of the silicon selective growth layers 110a and 110b. The second diffusion layer regions 107a and 107b are n-type impurity diffusion layers, and are electrically connected at underside edges to the first diffusion layer regions 106a and 106b of the same conductive type. The third diffusion layer regions 108a and 108b are provided in regions corresponding respectively to the silicon selective growth layers 110a and 110b of the silicon substrate 101. The third diffusion layer regions 108a and 108b are formed by diffusing the n-type impurities doped in the silicon selective growth layers 110a and 110b into the silicon substrate 101.
FIG. 15 is an impurity concentration profile of this transistor taken along a line A3-A4 in FIG. 14. In FIG. 15, the horizontal axis represents distance from the top faces of the silicon selective growth layers 110a and 110b, and the vertical axis represents the impurity concentration. A position R1 of the silicon selective growth layer 110b and a position R2 of the top face of the silicon substrate 101 are shown on the horizontal axis of FIG. 15. FIG. 15 indicates the impurity concentration S1 of the first diffusion layer (n− layer extension) region 106b, the impurity concentration S2 of the second diffusion layer (n+ layer) region 107b, the impurity concentration S3 of the third diffusion layer region 108b, and impurity concentration S4 of the fourth diffusion layer (p-type Halo) region 109b. Thus in this transistor, the impurity concentration S1 of the first diffusion layer regions 106a and 106b is lower than the impurity concentration S2 of the second diffusion layer regions 107a and 107b, and the impurity concentration S3 of the third diffusion layer regions 108a and 108b. The first diffusion layer regions 106a and 106b, the second diffusion layer regions 107a and 107b, and the third diffusion layer regions 108a and 108b constitute an LDD structure. That is, the second diffusion layer region 107a and the third diffusion layer region 108a, and the second diffusion layer region 107b and the third diffusion layer region 108b, which have high impurity concentration, respectively function as a source and a drain. The fourth diffusion layer regions 109a and 109b, which have low impurity concentration, function as extension regions.
The third diffusion layer regions 108a and 108b, which constitute a source and a drain, are formed by diffusion of n-type impurities doped in the silicon selective growth layers 110a and 110b into the silicon substrate 101. This enables the thickness (effective junction depth) of the third diffusion layer regions 108a and 108b to be thin. This transistor is therefore unlikely to suffer short channel effect Also, since the source and drain are constituted by the second diffusion layer regions 107a and 107b and the third diffusion layer regions 108a and 108b, their thicknesses become the total thicknesses of these diffusion layer regions, enabling resistance to be suppressed.
In this transistor, to achieve a reliable electrical connection between the first diffusion layer regions 106a and 106b and the second diffusion layer regions 107a and 107b, the impurity concentration of the portions of the second diffusion layer regions 107a and 107b that contact to the silicon substrate 101 (impurity concentration at point B in FIG. 15) must be high. However, when the impurity concentration at point B is high, more impurities are diffused to the silicon substrate 101, increasing the depth of the third diffusion layer regions 108a and 108b. 
In miniaturizing the transistor, the side walls 105 provided on the side walls of the gate electrode 103 also becomes thinner. Consequently, the distance between the third diffusion layer region 108a and the third diffusion layer region 108b tends to decrease. In this circumstance, if the third diffusion layer regions 108a and 108b are fabricated to a deep position from the top face of the silicon substrate 101, short channel effect is likely to happen. This makes it difficult to shorten the gate length, i.e. to miniaturize the transistor. For this reason, the third diffusion layer regions 108a and 108b are generally designed to be fabricated at the minimum depth required for electrical connection between the first diffusion layer regions 106a and 106b and the second diffusion layer regions 107a and 107b. 
However, the fourth diffusion layer regions 109a and 109b of the reverse-conductive type p-type) are generally provided below the first diffusion layer regions 106a and 106b and the third diffusion layer regions 108a and 108b. Therefore, if it is attempted to make the depth of the third diffusion layer regions 108a and 108b as shallow as possible, the p-type impurity in the fourth diffusion layer regions 109a and 109b cannot be repelled by the reverse-conductive impurity in the third diffusion layer regions 108a and 108b, leading to a high p-type impurity concentration at the interfaces between the fourth diffusion layer regions 109a and 109b and the third diffusion layer regions 108a and 108b. As a result, as indicated at point C in FIG. 15, a high-concentration pn junction is formed between the third diffusion layer regions 108a and 108b and the fourth diffusion layer regions 109a and 109b, and the junction capacity in the diffusion layer region greatly increases. This leads to a problem of signal delay in the circuit.
Due to the nature of fabricating diffusion layer regions, the size of the first diffusion layer regions 106a and 106b is determined by the width of the side walls 105. As already mentioned, when the side walls 105 become narrower as the transistor is miniaturized, the first diffusion layer regions 106a and 106b also become smaller. This lessens the effect of by the LDD structure, namely the electric field relaxation effect. This leads to a problem of reduced hot carrier (HC) immunity.